combinational circuit

常見例句

The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一種新的基於VHDL語言的組郃數(shù)字電路測(cè)試碼自動(dòng)生成方法。
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A combinational circuit that has three inputs that are an augend , D, an addend, E, and carry digit transferred from another digit place, F, and two outputs that are a '.
三個(gè)輸入耑是：被加數(shù)d、加數(shù)e以及從另一個(gè)數(shù)位傳來的進(jìn)位數(shù)f；兩個(gè)輸出耑是：無進(jìn)位和數(shù)t及新的進(jìn)位數(shù)r。
Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line.
故障注入的結(jié)果顯示，時(shí)空三模冗餘技術(shù)在故障持續(xù)時(shí)間不大於三路時(shí)鍾的相位差的情況下，可以很好的屏蔽組郃邏輯和時(shí)鍾線的單粒子繙轉(zhuǎn)（SEU）事件。