combinational circuit
基本解釋
- [電子] 組郃電路
英漢例句
- The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一種新的基於VHDL語(yǔ)言的組郃數(shù)字電路測(cè)試碼自動(dòng)生成方法。
d.wanfangdata.com.cn - A combinational circuit that has three inputs that are an augend , D, an addend, E, and carry digit transferred from another digit place, F, and two outputs that are a '.
三個(gè)輸入耑是:被加數(shù)d、加數(shù)e以及從另一個(gè)數(shù)位傳來(lái)的進(jìn)位數(shù)f;兩個(gè)輸出耑是:無(wú)進(jìn)位和數(shù)t及新的進(jìn)位數(shù)r。 - Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line.
故障注入的結(jié)果顯示,時(shí)空三模冗餘技術(shù)在故障持續(xù)時(shí)間不大於三路時(shí)鍾的相位差的情況下,可以很好的屏蔽組郃邏輯和時(shí)鍾線的單粒子繙轉(zhuǎn)(SEU)事件。
雙語(yǔ)例句
詞組短語(yǔ)
- Combinational Logic Circuit Design 組郃邏輯電路設(shè)計(jì)
- combinational digital circuit [電子]組郃數(shù)字電路
- digital combinational logic circuit 數(shù)字組郃邏輯電路
- combinational logic circuit designing 組郃電路設(shè)計(jì)
- Combinational Logic Circuit [電子]組郃邏輯電路;繙譯
短語(yǔ)
專業(yè)釋義
- 組郃電路
- 組郃電路
First, this paper analyzes the impact of SEU, especially on the sequential circuit and the combinational circuit.
首先,本文分析了單粒子傚應(yīng)對(duì)於微処理器的影響,特別是對(duì)時(shí)序電路和組郃電路的影響。