phase lock

基本解釋

The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
數(shù)字鎖相環(huán)路（DPLL）是數(shù)字相乾解調(diào)技術的核心。
Phase lock oscillator, address coding and intermission mode are taken to stabilize the system and to promise the targets working period longer than 10 day.
系統(tǒng)中採用了鎖相技術和地址編碼，竝採用間隙工作方式，使得本系統(tǒng)工作性能穩(wěn)定，目標源一次充電可連續(xù)工作10天以上。
This paper presents a digital process of quartz tuning-fork gyro. The process has tow function under the sparse sample. One is phase lock and frequency tracking of driving circuit.
設計了一種石英音叉陀螺的數(shù)字化算法，該算法在稀疏採樣的條件下實現(xiàn)了兩大功能：敺動環(huán)路的鎖相和頻率跟蹤；
d.wanfangdata.com.cn

The next phase is lock-in where users form usage habits.
FORBES: On Take-off Runway With A Chance of Runaway Growth: A Case of Social Products
For starters, the Russians will surely try to lock us into a "first phase NMD" along the lines of the single, ground-based site President Clinton ultimately chose not to start building in Alaska.
CENTERFORSECURITYPOLICY: Center For Security Policy

鎖相
The circuits used are Chua’circuit and phase lock loop.
所用的電路爲蔡氏電路和鎖相環(huán)電路。
相位同步
鎖柑

鎖相
The bit synchronizer proposed by this paper consists of integral filter, symbol period estimation circuit and digital phase lock loop circuit.
本文所提出的位同步器電路包括積分濾波、碼元重複頻率估計和數(shù)字鎖相三個部分。
相位同步
同相