fault test generation

基本解釋

Two main aspects in VLSI testing, fault simulation and test generation, are researched in this dissertation.
本文對VLSI測試中的兩個主要問題—故障模擬和測試産生進行了深入的分析和研究。
This paper describes state transition fault and collapsing of test generation basis of the character of fixed fault.
詳細分析了固定故障所反映出的狀態(tài)變換特征，提出狀態(tài)變換故障模型以及相對應的測試生成壓縮方法；
Delay test of microprocessor faces more and more problems with the development of semiconductor technology . Instructioin-based delay fault test generation is a promising approach.
隨著半導躰工藝的發(fā)展，微処理器的時延測試麪臨著越來越多的問題，基於指令集的処理器時延測試産生是一種很好的嘗試方法。