clock data recovery

基本解釋

The main circuits include a trans-impedance amplifier (TIA), a limiting amplifier, a clock and data recovery (CDR) unit, and a (1∶4) demultiplexer (DEMUX).
主要電路包括前置放大、限幅放大、時(shí)鍾恢複、數(shù)據(jù)判決和1∶4分接。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基於SERDES的串行通信過程中採用時(shí)鍾和數(shù)據(jù)恢複技術(shù)（CDR）代替同時(shí)傳輸數(shù)據(jù)和時(shí)鍾，從而解決了限制數(shù)據(jù)傳輸速率的信號(hào)時(shí)鍾偏移問題。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
在突發(fā)式的接收模塊中，邏輯電平的恢複和時(shí)鍾數(shù)據(jù)的恢複是其關(guān)鍵的問題。

clock and data recovery 時(shí)鍾數(shù)據(jù)恢複;時(shí)鍾與數(shù)據(jù)恢複;時(shí)鍾及數(shù)據(jù)恢複;複電路
Clock and Data Recovery Circuits 時(shí)鍾與數(shù)據(jù)恢複電路
parallel clock and data recovery 竝行時(shí)鍾數(shù)據(jù)恢複
Clock and Data Recovery Circuit 複電路;時(shí)脈與資料廻複電路
clock and data recovery cdr 時(shí)鍾和數(shù)據(jù)恢複