adder subtracter

基本解釋

A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.
根據供給它的控制信號，或起加法器作用或起減法器作用的一種邏輯元件。
The subtracter (230) calculates the difference between the output of the adder (250) and the quantized value of the output of the adder (250) to determine the quantization error.
減法器（230）計算加法器（250）的輸出和加法器（250）的輸出的量化值之間的差以便確定量化誤差。
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