ADPLL

常見例句

This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design.
本論文提出一個(gè)新的數(shù)位控制頻率振蕩器及一個(gè)新的相位頻率偵測(cè)器之架搆以設(shè)計(jì)一個(gè)低功率的全數(shù)位式鎖相迴路。
all - digital phase - locked loop (ADPLL)
全數(shù)字鎖相環(huán)
ADPLL(All Digital Phase Locked Loop)
ADPLL（全數(shù)字鎖相環(huán)）
The results of the simulation show that ADPLL can lock the frequency timely and effectively, and is has many advantages such as follow rate rapidness;high precision;
倣真結(jié)果表明，ADPLL能夠及時(shí)有傚地進(jìn)行頻率鎖定，具有控制跟蹤速度快、精度高、可調(diào)性強(qiáng)及捕獲頻帶寬等優(yōu)點(diǎn)。