synchronizing circuit

基本解釋

Design of a Circuit Synchronizing the Byte Clock with the Parallel Data in the Deserializer;
在串并轉(zhuǎn)換接收器中，并行數(shù)據(jù)在字節(jié)時鐘的作用下并行輸出。
A synchronizing nonalltonomus chaotic circuit is presented with RC-QP Amp. It can be used to demonstrate experiment teaching of chaotic theory.
本文給出一種用普通的電阻、電容和運算放大器實現(xiàn)的非自治混沌信號發(fā)生器電路，適用于進行混沌理論的演示實驗教學。
In the circuit design, unit current source arrays and digital synchronizing cells are used to improve the matching and dynamic range of DAC.
電路設計中使用單位電流源陣列和數(shù)字同步控制單元來提高電流源的匹配性和動態(tài)范圍；