pipelined analog-to-digital converter

基本解釋

A 13bit, pipelined analog-to-digital converter(ADC)designed to achieve high linearity is described.
介紹了一個(gè)采用多種電路設(shè)計(jì)技術(shù)來實(shí)現(xiàn)高線性13位流水線A/D轉(zhuǎn)換器。
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described .
設(shè)計(jì)了一個(gè)用于流水線型模數(shù)轉(zhuǎn)換器的低壓采樣保持電路。
To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter(ADC), a new statistics-based background calibration technique is presented.
為了降低流水線模數(shù)轉(zhuǎn)換器中數(shù)字校準(zhǔn)電路的規(guī)模和功耗，提出了一種新的基于信號(hào)統(tǒng)計(jì)規(guī)律的后臺(tái)數(shù)字校準(zhǔn)技術(shù)。