logic-level simulation

常見例句

雙語例句

• This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
  介紹了VHDL邏輯級模擬系統(tǒng)中模擬模塊的設(shè)計和實現(xiàn)。
• With appropriate tool support, designers could perform execution or simulation and debugging on high-level system models to validate and verify system logic early on.
  有了適當?shù)墓ぞ咧С郑O(shè)計人員可以在高層的系統(tǒng)模型上進行執(zhí)行或模擬，并調(diào)試，從而在早期確認并驗證系統(tǒng)邏輯。
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