logic gate level

基本解釋

Using gate level modeling might not be a good idea for any level of logic design.
使用門級建模對于任何邏輯設計都不是一個好的設計。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速單元采用帶有電平恢復的傳輸管邏輯實現(xiàn)，高速單元采用動態(tài)傳輸門邏輯實現(xiàn)。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此門陣列采用的BFL預功能級標準邏輯單元，具有九種組合邏輯功能及兩種不同選擇的驅動能力，并具有輸出電平調節(jié)功能。