bus interface controller

常見(jiàn)例句

The PCI top-level block design is first presented in terms of the bus interface controller.
在分析PCI總線接口控制器基本功能的基礎(chǔ)上，給出其頂層設(shè)計(jì)。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
根據(jù)PCI總線操作時(shí)序，提出了從設(shè)備接口控制器的有限狀態(tài)機(jī)模型。
PCI bus is high bandwidth, being independent of CPU, high capacity bus. The bus interface controller design is its key techniques to application .
PCI總線是一種高帶寬、獨(dú)立于CPU的高性能總線，總線接口控制器的設(shè)計(jì)是其應(yīng)用的關(guān)鍵所在。