buffer lookaside

基本解釋

The use of large pages can also improve performance by reducing the number of translation lookaside buffer (TLB) misses.
大內(nèi)存頁的使用還可以通過減少變換索引緩沖（translation lookaside buffer, TLB）的失敗次數(shù)來提高性能。
To speed up address translation, there is a processor-on-a-chip (PoC) cache and associated logic called translation lookaside buffer (TLB).
為了加快地址轉(zhuǎn)換，架構(gòu)中有一個(gè) processor-on-a-chip (PoC) 緩存和相關(guān)的轉(zhuǎn)換后備緩沖器 (TLB) 邏輯。
The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.
評(píng)測(cè)表提供為特定的處理器事件收集的采樣的百分?jǐn)?shù)或數(shù)量，比如高速緩存線路故障的數(shù)量、傳輸后備緩存( TLB )故障的數(shù)量，等等。