branch target buffer

基本解釋

The fetcher also generates a search address for output to the branch target buffer.
指令讀取器亦產(chǎn)生搜尋位址輸出至分支目標(biāo)緩沖器中。
The branch target buffer is provided with a tag RAM that is organized in a set associative fashion.
分支目標(biāo)緩沖器提供一個(gè)架構(gòu)成集合相關(guān)式的標(biāo)簽…
Using system simulator, we synthetized the effect of the prediction scheme and the branch target buffer. The conclusion is useful to the single-issue-pipeline microprocessor design.
實(shí)驗(yàn)基于系統(tǒng)級模擬器，綜合轉(zhuǎn)移預(yù)測策略和轉(zhuǎn)移目標(biāo)緩沖器行為進(jìn)行完整模擬，結(jié)論對于其它采用單發(fā)射流水線結(jié)構(gòu)的微處理器設(shè)計(jì)具有較好的借鑒意義。